ïÔ: D&R SoC News Alert [SoC-NewsAlert@design-reuse.com]
ïÔÐÒÁ×ÌÅÎÏ: 15 ÍÁÒÔÁ 2005 Ç. 14:39
ëÏÍÕ: Michael Dolinsky
ôÅÍÁ: D&R SoC News Alert - March 15, 2005
DR SoC News Alert
Design And ReuseDesign And ReuseDesign And Reuse
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March 15, 2005    


Michael,
Welcome to the issue of March 15, 2005 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

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MD5, SHA-1 and SHA-256 core capable of 2000 Mbps Throughput from Elliptic Semiconductor
Dual 10-bit 80 MSPS DAC in TSMC 0.13um from Nordic Semiconductor
Silicon-proven IP for Public Key Acceleration from SafeNet
SATALink Device side with ARM AMBA bus from Silicon Image
USB Hi-Speed On-The-Go Controller for Multiple Devices Core from CAST
OCP 2.0 SystemVerilog Assertion Checker from HDL Design House
USB2.0 OTG LS-FS-HS 3.3V-1.2V-1.2V UTMI+ TSMC 0.13 from ChipIdea Microelectronics
Debugging SoC Designs with Transactions
Compilers Enable Embedded Comm Application Optimization
Design of SystemVerilog Assertion IP
A methodology for DSP-based FPGA design
Why does STMicroelectronics license in FPGA blocks?
Panelists peer into future of FPGAs
Design outsourcing a challenge
IP/SOC PRODUCTS
MindTree to demonstrate its Bluetooth capabilities on OMAP and Nucleus at CTIA Wireless 2005
Arteris introduces industry's first products for building networks on Chip (NoC)
M2000 unveils optimized eFPGA architecture for DSP functions
HiTech Global Distribution expands IP Portfolio with SDIO Core
TransChip and CEVA Collaborate to Create Highly Compact Video Streaming Solution for Multimedia Applications
Falanx Announces Availability of Geometry Processors for Mobile Gaming
Memec Unique Announces Multi-Channel UART Evaluation Kit for Actel ProASIC Plus
Falanx Submits Mali IP Cores to Khronos OpenGL ES Conformance Process
Toshiba Launches Family of SATA PHY Cores That Meet High Speed Requirements of Storage, Networking and Consumer Markets
STRUCTURED ASIC
LSI Logic Introduces RapidChip Xtreme2(TM) Family With Unprecedented SERDES Integration and I/O Bandwidth
DEALS
MoSys 1T-SRAM IP Ships in HUDSON Soft's Video Game Controller; Video Game Controller in Volume Production Targets Toy Markets
NEC Electronics America Expands ASIC IP Portfolio with Tensilica’s Xtensa Configurable Processor
CEVA-TeakLite DSP License Extended By STMicroelectronics For Next Generation DSL Central Office Chipsets
Further contract successes for new HyperSpeed and HyperLength FFT cores from RF Engines
Micronas Micronas Licenses Silicon Image's HDMI and DVI IPLicenses Silicon Image's HDMI and DVI IP
Virage Logic's High-Density ASAP Memory(TM) IP Used in Development of Low-leakage Wireless Multimedia Processors From NVIDIA
Legerity Selects StarCore Technology to Power Its Next Generation VoIP and FTTP Products
BUSINESS
Digital Core Design will take part in the EU Gateway to Japan
Tensilica Expands Into China
QuickSilver closes operations, shops IP
FINANCIAL RESULTS
Actel Corporation Announces First Quarter Business Update
Faraday Monthly Sales Report -- February 2005
Xilinx Updates Guidance for March Quarter FY05
LEGAL
U.S. District Judge Rules to Disqualify Patriot Scientific Corporation's Counsel and to Deny Witness Testimony
EMBEDDED SYSTEMS
STMicroelectronics Introduces Highly Integrated Microcontroller with Embedded Programmable Logic for Wireless Infrastructure Applications
Atmel's New Single-Cycle 8051 Core Provides Big Performance Boost and Low Power
FS2 System Navigator Delivers Multi-Core Debugging for Tensilica Xtensa Processors
FS2 Introduces System Navigator with PDtrace for MIPS32 24K Debug
FOUNDRIES
TSMC's sales falls 18% amid silicon foundry lull
TSMC Monthly Sales Report - February 2005
FPGA/CPLD
Industry Study Reaffirms Reliability of Actel FPGAs Against Radiation-Induced Failures
Xilinx Ships Virtex-4 SX55 - World's Fastest FPGA For DSP
EDA
ZAiQ Technologies and ProDesign Integrate High Speed Transaction-Based Verification System
Synopsys' coreAssembler Reduces Time and IP Integration Risk for Spirit-Compliant IP
OTHER
Rambus Demonstrates Its 800MHz DDR2 Memory Controller Interface At Denali MemCon In Taiwan
Research centre for SoC opens in Belfast

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